Enjoy your life at every moment

           Once a fisherman was sitting near seashore, under the shadow of a tree smoking his beedi. Suddenly a rich businessman passing by approached him and enquired as to why he was sitting under a tree smoking and not working. To this the poor fisherman replied that he had caught enough fishes for the day.

Hearing this the rich man got angry and said: Why don’t you catch more fishes instead of sitting in shadow wasting your time?

Fisherman asked: What would I do by catching more fishes?

Businessman: You could catch more fishes, sell them and earn more money, and buy a bigger boat.

Fisherman: What would I do then?

Businessman: You could go fishing in deep waters and catch even more fishes and earn even more money.

Fisherman: What would I do then?

Businessman: You could buy many boats and employ many people to work for you and earn even more money.

Fisherman: What would I do then?

Businessman: You could become a rich businessman like me.

Fisherman: What would I do then?

Businessman: You could then enjoy your life peacefully.

Fisherman: Isn’t that what I am doing now?

Moral – You don’t need to wait for tomorrow to be happy and enjoy your life. You don’t even need to be more rich, more powerful to enjoy life. LIFE is at this moment, enjoy it fully.

As some great men have said “My riches consist not in extent of my possessions but in the fewness of my wants”.

Xilinx tips and tricks

Problem1: ISE does not start

Solution:

  Clean up the project files. In order to do that go to "Project>Cleanup Project Files" as instructed in the following picture and in pop-up click ok. Note that this will delete those files instead of just removing them from your project.

  Open the task manager, kill redundant ISE processes. Press Alt-Ctrl-Del and look in the processes tab for "ise.exe". If there are more than one instances the chances are that something is wrong. Kill one of them.

Problem2: Whenever I try to add a file to the project, I get a weird error.

Solution: Make sure there are no spaces in the project path and the path of the file you want to add (Desktop is a symbolic link to C:\Documents and Settings\user_name\Desktop and therefore has spaces; avoid it). Xilinx is notorious for not being able to parse paths containing spaces. So don't ask for trouble.

Problem3: Whenever I start ISE simulator the clock is set to high impedance (Z) even if I have properly set it up.

Solution: It seems like you are simulating the wrong file. Make sure that the testbench is selected in your sources window and not the UUT (unit under test).

Problem4: My simulation starts correctly but I can not observe the internal signals of my UUT?

Solution: To add the signals you need choose the module first. The signals objects related to this module is displayed under the objects window. Then right click on the signals of your choice and click "Add to Wave Window". Altenatively you can drag and drop the signals to the Simulation/Waveform window. If you want to select all the signals of a module right click on a module in the Instances tab and click "Add to the Wave Window". If you want to view the data bus values in hex instead of binary, right click on the signal in the wave window. Select �Radix->Hexadecimal�.

Problem5: Place and Route fails with ERROR:Par:228 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint.

Solution: The timing constraints you have set are too tight and impossible to meet. You need either to set higher period target in your timing constraints.

Problem6: Random Xilinx weirdness. While you work Xilinx reports an error and dies immediately.

Solution: Many things could have gone wrong. The most common one is that the tool has corrupted your project files. In this case, it is better to give up on your current project and start a new one from the beginning. Open a previous project (.ise file) which you know to be working and start a new project by adding the .v files you used. You should always prefer to add and copy the sources of the files into your project ( "Add Copy of Source" over "Add source" when you right click on the project ).

Problem7: How do I save the ISIM settings and automatically load it?

Solution: As seen in the picture below, suppose you change the radix so that the values in the waveform are shown in decimal.

In order to make this a default part of my simulation,

1. First saved the Wave Configuration file (wcfg) to the hard drive by using the "save as" option under the file menu.

2. Back in ISE, under simulation source, right click on "Simulate Behavioral Model", choose "Process Properties"

3. Enable "Use Custom Waveform Configuration File"

4. Under "Custom Waveform Configuration File" use browse to select the file you saved your configuration to in ISIM

5. Click ok to close the dialog and you are done.

On your next simulation, you should see the results displayed using the setting you saved.

SystemVerilog

SystemVerilog is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, and reusability of Verilog based code. SystemVerilog brings a higher level of abstraction to design and verification. The language enhancements in SystemVerilog provide more concise hardware descriptions, while still providing an easy route with existing tools into current hardware implementation flows.

SystemVerilog provides a complete verification environment, employing Directed and Constraint Random Generation, Assertion Based Verification and Coverage Driven Verification. These methods improve the verification process dramatically.

SystemVerilog also provides enhanced hardware-modeling features, which improve the RTL design productivity and simplify the design process.       

Advantages of Using SystemVerilog:

» SystemVerilog was adopted as a standard by the Accellera organization, and is approval by IEEE. These ensure a wide embracing and support by multiple vendors of EDA tools and verification IP's, as well as interoperability between different tools and vendors.

» Since SystemVerilog is an extension of the popular Verilog language, the adoption process of SystemVerilog by engineers is extremely easy and straightforward. SystemVerilog enables engineers to adopt a modular approach for integrating new modules into any existing code. As a result, the risks and costs of adopting a new verification language are reduced.

» Being an integrated part of the simulation engine, eliminates the need for external verification tools and interfaces, and thus ensures optimal performance (running at least x2 faster than with any other verification languages).

» SystemVerilog brings a higher level of abstraction to the Verilog designer. Constructs and commands like Interfaces, new Data types (logic, int), Enumerated types, Arrays, Hardware-specific always (always_ff, always_comb) and others allow modeling of RTL designs easily, and with less coding.

» SystemVerilog extends the modeling aspects of Verilog by adding a Direct Programming Interface which allows C, C++, SystemC and Verilog code to work together without the overhead of the Verilog PLI.

Dynamic Arrays

Why Dynamic Arrays       Verilog allows one-dimensional arrays of variables all along and Verilog-2001 allows multi-dimensional ones too. SystemVerilog classifies an array as 'packed' or 'unpacked' depending on how it is declared. If the array upper and lower bounds are declared between the variable type and the variable name, such as reg [7:0] a_reg_array; The array is called packed. If the array bounds are declared after the variable name, it is called an unpacked array, such as, int int_array [7:0]; Of course, an array may have both packed and unpacked parts. reg [7:0] reg_array [3:0][7:0]; Whether you are declaring packed or unpacked arrays of whatever dimensions, one thing that remains common is they are all static declarations. Once an array is declared this way, the tool that parses the declaration will statically allocate memories for the array and there is no way that you can alter that afterwards. As a result, the size of an array, for example, cannot be changed once it is declared. There are occasions, however, when you would want to declare an array whose size cannot be pre-determined. A temporary buffer for variable rate incoming data stream, a list that has variable number of elements are few examples of problems that need array size that needs to be changed dynamically. Using a very large array with the assumption that it can hold the largest data (yet whose size is unknown) is neither safe nor efficient. So, the question is how can we declare an array whose size is dynamically alterable? SystemVerilog dynamic array type addresses this need. In a sense, dynamic arrays are equivalent of malloc library function in C that allows one to dynamically alter the size of an array (or pointer). Declaring a Dynamic Array             A dynamic array lets you keep the number of elements in the array unspecified at the declaration time. You can define the number of elements it holds during run time. Moreover, once declared, the number of elements can be altered at a later point of time too. However, these benefits come at a price. There are some limitations on dynamic arrays. These limitations are: The dynamic part of the array must be of unpacked nature. A packed array cannot be dynamic (can you guess why?)