BASIC GATES USING 2:1 MUX

The following post shows the implementation of basic gates using 2:1 mux! 

It helps often in written tests and interview process! 

The idea can be extended to implement other logics like full adder, half adder and also to multiplying logic! 

Xilinx tips and tricks

Problem1: ISE does not start

Solution:

  Clean up the project files. In order to do that go to "Project>Cleanup Project Files" as instructed in the following picture and in pop-up click ok. Note that this will delete those files instead of just removing them from your project.

  Open the task manager, kill redundant ISE processes. Press Alt-Ctrl-Del and look in the processes tab for "ise.exe". If there are more than one instances the chances are that something is wrong. Kill one of them.

Problem2: Whenever I try to add a file to the project, I get a weird error.

Solution: Make sure there are no spaces in the project path and the path of the file you want to add (Desktop is a symbolic link to C:\Documents and Settings\user_name\Desktop and therefore has spaces; avoid it). Xilinx is notorious for not being able to parse paths containing spaces. So don't ask for trouble.

Problem3: Whenever I start ISE simulator the clock is set to high impedance (Z) even if I have properly set it up.

Solution: It seems like you are simulating the wrong file. Make sure that the testbench is selected in your sources window and not the UUT (unit under test).

Problem4: My simulation starts correctly but I can not observe the internal signals of my UUT?

Solution: To add the signals you need choose the module first. The signals objects related to this module is displayed under the objects window. Then right click on the signals of your choice and click "Add to Wave Window". Altenatively you can drag and drop the signals to the Simulation/Waveform window. If you want to select all the signals of a module right click on a module in the Instances tab and click "Add to the Wave Window". If you want to view the data bus values in hex instead of binary, right click on the signal in the wave window. Select �Radix->Hexadecimal�.

Problem5: Place and Route fails with ERROR:Par:228 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint.

Solution: The timing constraints you have set are too tight and impossible to meet. You need either to set higher period target in your timing constraints.

Problem6: Random Xilinx weirdness. While you work Xilinx reports an error and dies immediately.

Solution: Many things could have gone wrong. The most common one is that the tool has corrupted your project files. In this case, it is better to give up on your current project and start a new one from the beginning. Open a previous project (.ise file) which you know to be working and start a new project by adding the .v files you used. You should always prefer to add and copy the sources of the files into your project ( "Add Copy of Source" over "Add source" when you right click on the project ).

Problem7: How do I save the ISIM settings and automatically load it?

Solution: As seen in the picture below, suppose you change the radix so that the values in the waveform are shown in decimal.

In order to make this a default part of my simulation,

1. First saved the Wave Configuration file (wcfg) to the hard drive by using the "save as" option under the file menu.

2. Back in ISE, under simulation source, right click on "Simulate Behavioral Model", choose "Process Properties"

3. Enable "Use Custom Waveform Configuration File"

4. Under "Custom Waveform Configuration File" use browse to select the file you saved your configuration to in ISIM

5. Click ok to close the dialog and you are done.

On your next simulation, you should see the results displayed using the setting you saved.

SystemVerilog

SystemVerilog is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, and reusability of Verilog based code. SystemVerilog brings a higher level of abstraction to design and verification. The language enhancements in SystemVerilog provide more concise hardware descriptions, while still providing an easy route with existing tools into current hardware implementation flows.

SystemVerilog provides a complete verification environment, employing Directed and Constraint Random Generation, Assertion Based Verification and Coverage Driven Verification. These methods improve the verification process dramatically.

SystemVerilog also provides enhanced hardware-modeling features, which improve the RTL design productivity and simplify the design process.       

Advantages of Using SystemVerilog:

» SystemVerilog was adopted as a standard by the Accellera organization, and is approval by IEEE. These ensure a wide embracing and support by multiple vendors of EDA tools and verification IP's, as well as interoperability between different tools and vendors.

» Since SystemVerilog is an extension of the popular Verilog language, the adoption process of SystemVerilog by engineers is extremely easy and straightforward. SystemVerilog enables engineers to adopt a modular approach for integrating new modules into any existing code. As a result, the risks and costs of adopting a new verification language are reduced.

» Being an integrated part of the simulation engine, eliminates the need for external verification tools and interfaces, and thus ensures optimal performance (running at least x2 faster than with any other verification languages).

» SystemVerilog brings a higher level of abstraction to the Verilog designer. Constructs and commands like Interfaces, new Data types (logic, int), Enumerated types, Arrays, Hardware-specific always (always_ff, always_comb) and others allow modeling of RTL designs easily, and with less coding.

» SystemVerilog extends the modeling aspects of Verilog by adding a Direct Programming Interface which allows C, C++, SystemC and Verilog code to work together without the overhead of the Verilog PLI.

Dynamic Arrays

Why Dynamic Arrays       Verilog allows one-dimensional arrays of variables all along and Verilog-2001 allows multi-dimensional ones too. SystemVerilog classifies an array as 'packed' or 'unpacked' depending on how it is declared. If the array upper and lower bounds are declared between the variable type and the variable name, such as reg [7:0] a_reg_array; The array is called packed. If the array bounds are declared after the variable name, it is called an unpacked array, such as, int int_array [7:0]; Of course, an array may have both packed and unpacked parts. reg [7:0] reg_array [3:0][7:0]; Whether you are declaring packed or unpacked arrays of whatever dimensions, one thing that remains common is they are all static declarations. Once an array is declared this way, the tool that parses the declaration will statically allocate memories for the array and there is no way that you can alter that afterwards. As a result, the size of an array, for example, cannot be changed once it is declared. There are occasions, however, when you would want to declare an array whose size cannot be pre-determined. A temporary buffer for variable rate incoming data stream, a list that has variable number of elements are few examples of problems that need array size that needs to be changed dynamically. Using a very large array with the assumption that it can hold the largest data (yet whose size is unknown) is neither safe nor efficient. So, the question is how can we declare an array whose size is dynamically alterable? SystemVerilog dynamic array type addresses this need. In a sense, dynamic arrays are equivalent of malloc library function in C that allows one to dynamically alter the size of an array (or pointer). Declaring a Dynamic Array             A dynamic array lets you keep the number of elements in the array unspecified at the declaration time. You can define the number of elements it holds during run time. Moreover, once declared, the number of elements can be altered at a later point of time too. However, these benefits come at a price. There are some limitations on dynamic arrays. These limitations are: The dynamic part of the array must be of unpacked nature. A packed array cannot be dynamic (can you guess why?)

Solving error in xilinx

How to solve the following error in Xilinx ISE:
"Simulator: 702 – Can’t find design unit xxx in library work located at isim/work"
You can try two methods to solve this error:

1) Go to main menu -> Project -> Cleanup Project files. Click 'ok'. Now run the simulation again. If the error is still on then go to step 2.

  Note:-Cleaning up project files removes the generated synthesis and implementation files from the current project directory. This operation is final and you can not undo this procedure after you perform it. If you want to avoid loss of data, then create a backup copy of the project. For creating a backup for your project:
    Select Project > Take Snapshot. 
    In the Take a Snapshot of the Project dialog box, enter a name for your snapshot in the Snapshot Name field.
    In the Comment field, add any notes related to this version of your project. Comments are optional.
    Click OK.

2) Create a new project and add all the files in your current project to the new project.Now simulate the design. It should work now.

Verilog Modules

Hello friends,

I am here again with a new post.

We are very familiar with verilog coding but still have so many doubts

It's really interesting to know new things and new ways of coding.

But to master in coding we need to have sufficient backup (data) with us.

So here I am providing some links which, I feel, are useful to us in improving our coding style and also help in clarifying our doubts regarding coding.

Use them and improve the coding style...

http://web.engr.oregonstate.edu/~traylor/ece474/lecture_verilog/beamer/verilog_modules.pdf

How to use coe file for initializing BRAM

   Normally we initialize all the memory locations in a BRAM to zero using the "Fill Remaining memory locations" option in core generator. But this article will tell you how to use coe file as an initialization vector. Follow the steps:

1) Create a BRAM of depth = 16 and read and write width = 8 bits.
2) Check the "Load Init File" under the "Memory Initialization" option. Also select the file named "bram_contents.coe".
3) Before clicking on the generate button create a new file named bram_contents.coe and paste the following contents into it:
memory_initialization_radix=10;
memory_initialization_vector=1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16;
In the above text radix means the raidx of the data. I have written decimal data in the vector so my radix is "10". If you want to give the memory contents in binary form then change the coe file like this:

memory_initialization_radix=2;

memory_initialization_vector=0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111;
4) Now click on the generate button.

Tips for running a successful simulation in Xilinx ISim.

        This article covers some basics about running your simulation in Xilinx ISim. It will point out some basic mistakes people do when simulating their code in ISim.

Let’s go step by step, see the images for easier understanding of the steps. Open the images in a new tab in your browser if they are not clear enough.

1) Once the coding is done (both the test bench and the design to be tested) make sure you select the top entity (test bench code) in the Xilinx window as shown below. Many people just select any other file and click the compilation button.
Note down the red markings in the image below. Points to be noted are:

·                     Choose View as simulation.

·                     Select the top entity i.e. the test bench. If the wrong file is selected for simulation then the waveform in ISim will be blank and you will see no waveform.

·                     Double click on the Behavioral check syntax for compiling the design or for finding out any syntax errors.

·                     If the above step is successful then double click on Simulate Behavioral Model. If there are syntax errors in step 3 then you may have to check your code.

Some tips on reducing power consumption in Xilinx FPGA's

Power estimation and power reduction is an important part of any design. Especially in wireless devices, the reduction in power is a very important factor. In this article I will note down some points, on how to reduce the power consumption for xilinx based designs.

   1)  BRAM Enable signal:

Every BRAM has an enable signal which by default is high always. Most of the HDL coders never care to disable it even when the BRAM is not used. But when this enable signal is ON BRAM consumes a lot of power. It doesn't matter whether you change the address or write the data. So always have a control logic which will control the bram enable signal.

   2)  Low power option in coregen for BRAM's:

You can create a BRAM entity file using Xilinx's Core generator software. There are several options available in coregen to help you achieve what you want. For low power designs select the "Low power" option in coregen.

   3)  Decide on LUT or BRAM:

Suppose you want instantiate a memory in your design. Rather than going straight at BRAM or LUT, give it some thought. Xilinx says that for small memory blocks (less than 4 Kbits) LUT consumes less power than BRAM. Similarly for large memory blocks (more than 4 Kbits) BRAM uses less power for its operation than LUT-RAM. So from design to design, switch to LUT-RAM or BRAM depending on the size of memory block.

Synthesised code is too big for the fpga device - What to do?

Synthesised code is too big for the fpga device - What to do?

After lot of hard work you completed your HDL project. The simulation results verified that the code is functionally working. To check how it performs in hardware you synthesis the design. To your bad luck you realize that the code you just wrote is too big for the fpga. What can you do? Don't panic. There are few ways you can tackle this problem.

    1)  If possible choose a higher graded fpga device:

It’s a simple but the easiest thing you can do. Check if the lab or a friend has a better fpga device which can afford your design. If you really don't want to test the design in hardware, but just want to see the synthesis results then simply select the largest device available in the list.

2) Is the fpga out of pins?

Sometimes the synthesis tool will give out an "Out of resources" warning if the design has too many signals in its port list that the device can't support. This happens when you try to input or output large arrays or vectors.

In such cases use a multiplexed input or output system. Rather than inputting everything in one go, do it step wise

3) Changing synthesis tool settings:

By default, the synthesis tool try to optimize your design for both speed and resource usage. But you can change this setting so that the tool will optimize for less resource usage. This may reduce the speed a little, but may significantly reduce the resource usage.

FPGAs 'vs.' ASICs Basic Idea

FPGAs 'vs.' ASICs - Basic Idea

The debate on FPGAs vs ASICs has been around for quite a while now, but not without a good reason. The choice could have a significant bearing on the success of your product.
    What you will find below is one opinion of this long in vogue debate, by Vijayakumar Regupathi and Manisha Mankar,  architects - digitaldesign, at Robert Bosch Engineering and Business Solutions.

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We will hold our jump into the debate, in order to first define the two entities to be discussed. The Field-Programmable Gate Array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing—hence the "field-programmable" prefix. On the other hand, an Application-Specific Integrated Circuit (ASIC) is an integrated circuit customized for a particular use, rather than intended for general-purpose use. FPGAs and ASICs can both be configured using the Hardware Description Language (HDL), and most logic functions that an ASIC can perform, can be implemented in an FPGA as well.

How did it all begin?
A little bit on the background will help to set the context for our discussion. In the bygone era, IP routers were, by a great extent,

The basics of FPGA mathematics

One of the many benefits of an FPGA-based solution is the ability to implement a mathematical algorithm in the best possible manner for the problem at hand. For example, if response time is critical, then we can pipeline the stages of mathematics. But if accuracy of the result is more important, we can use more bits to ensure we achieve the desired precision. Of course, many modern FPGAs also provide the benefit of embedded multipliers and DSP slices, which can be used to obtain the optimal implementation in the target device.

Let’s take a look at the rules and techniques...

How to Implement STATE MACHINES on FPGA

State machines are often the backbone of FPGA development. Choosing the right architecture and implementation methods will ensure that you obtain an optimal solution.

Refer to the following link for the full article....

How to Implement State Machines on FPGA