TRANSPOSE OF A MATRIX

The following code is to get the transpose of a matrix. I have taken a simple 2x2 matrix. The logic in finding the transpose is similar to the logic in C. The code is written using procedural statements. The $display functions are used for the output display. The testbench for the program is also provided after the code.

Code:

module mat_add(

 input clk,

 input [7:0] in_1,

 input [7:0] in_2,

 input [7:0] in_3,

 input [7:0] in_4,

 output  [31:0] given_in,

 output  [31:0] trans_out

);

wire [7:0] temp [1:0][1:0];

wire [7:0] trans_temp [1:0][1:0];

genvar ROW,COLUMN;

assign temp[0][0] = in_1;

assign temp[0][1] = in_2;

assign temp[1][0] = in_3;

assign temp[1][1] = in_4;

for (COLUMN=0;COLUMN<2;COLUMN=COLUMN+1) begin

for (ROW=0;ROW<2;ROW=ROW+1) begin

assign trans_temp[COLUMN][ROW] = temp[ROW][COLUMN];

end

end

initial

begin

#100$display("the original matrix");

#100$display("%b\t %b",temp[0][0],temp[0][1]);

#100$display("%b\t %b",temp[1][0],temp[1][1]);

#100$display("the transposed matrix");

#100$display("%b\t %b",trans_temp[0][0],trans_temp[0][1]);

#100$display("%b\t %b",trans_temp[1][0],trans_temp[1][1]);

end

assign given_in = {{temp[1][1]},{temp[1][0]},{temp[0][1]},{temp[0][0]}};

assign trans_out = {trans_temp[0][0],trans_temp[0][1],trans_temp[1][0],trans_temp[1][1]};

endmodule

Testbench:

module matrix_transpose_test;

                // Inputs

                reg clk;

                reg [7:0] in_1;

                reg [7:0] in_2;

                reg [7:0] in_3;

                reg [7:0] in_4;

                // Outputs

                wire [31:0] given_in;

                wire [31:0] trans_out;

                // Instantiate the Unit Under Test (UUT)

                mat_add uut (

                                .clk(clk),

                                .in_1(in_1),

                                .in_2(in_2),

                                .in_3(in_3),

                                .in_4(in_4),

                                .given_in(given_in),

                                .trans_out(trans_out)

                );

                initial begin

                                // Initialize Inputs

                                clk = 0;

                                in_1 = 0;

                                in_2 = 0;

                                in_3 = 0;

                                in_4 = 0;

                                // Wait 100 ns for global reset to finish

                                #100;

                                clk = 1;

                                in_1 = 8'd12;

                                in_2 = 8'd23;

                                in_3 = 8'd45;

                                in_4 = 8'd32;

                                // Add stimulus here

                end

      endmodule

Output:

the original matrix

00001100     00010111

00101101     00100000

the transposed matrix

00001100    00101101

00010111    00100000

Example of multidimensional array

The following code is a best example for declaring a multi-dimensional array. It gives you an idea on how to declare a one dimensional and a two dimensional array. The code is based on system verilog which allows you to declare an array without specifying the length (in the following code reg [15:0] len_type []). 

module multidimensional_array();

reg [7:0] preamble [0:6] = '{8'hAA,8'hAA,8'hAA,8'hAA,8'hAA,8'hAA,8'hAA};

reg [7:0] dest_src_addr [0:1] [0:5] = '{'{8'h0,8'h1,8'h2,8'h3,8'h4,8'h5},'{8'h6,8'h7,8'h8,8'h9,8'hA,8'hB}};

reg [15:0] len_type [];

initial begin

$display("example of multidimensional array\n");

$display ("preamble[0]= %b", preamble[0]);

$display ("preamble[1][0]= %b", preamble[1][0]);

$display ("dest_src_addr[0][1]= %b", dest_src_addr[0][1]);

$display ("dest_src_addr[1][1]= %b\n", dest_src_addr[1][1]);

len_type = new[2];

for ( int i = 0; i < 2; i ++)

begin

len_type[i] = i;

end

#1 $finish;

end

endmodule

Output :

Example of multidimensional array

preamble[0]= 10101010

preamble[1][0]= 0

dest_src_addr[0][1]= 00000001

dest_src_addr[1][1]= 00000111

         Here is a simple notes on Verilog operators. It gives a brief details of all operators used in verilog. Hope this is useful.

Verilog Operators..

verilog notes....

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