Here is the list of FPGA based VLSI projects ideas for experimenting with VHDL and Verilog HDL, for final year projects of electronics engineering.
• VLSI Design Of Two Wire Serial EEPROM for Embedded Microcontrollers Specification
• VLSI Design of Diminished-One Modulo 2n + 1 Adder using Circular Carry Selection
• VLSI Design of DES (Data Encryption Standard) Algorithm
• VLSI Design and Implementation of Water Pump Controller using VHDL/Verilog HDL
• VLSI Design and Implementation of Stepper Motor Controller
• VLSI Design and Implementation of Solar Panel Control
• VLSI Design and Implementation of Robot Controller
• VLSI Design and Implementation of I2C Controller Core
• VLSI Design and Implementation of Home Appliances Control Designing
• VLSI Design and Implementation of Fuzzy Controller Design
• VLSI Design and Implementation of FIR and LIR Designing
• VLSI Design and Implementation of Encryption and Decryption using VHDL/Verilog HDL
• VLSI Design and Implementation of MP3 Encoder & Decoder using VHDL/Verilog HDL
• VLSI Design and Implementation of Electronic Voting Machine
• VLSI Design and Implementation of Electronic Automation using VHDL/Verilog HDL
• VLSI Design and Implementation of DMA using VHDL/Verilog HDL
• VLSI Design and Implementation of Data Routing Multiplexer using VHDL/Verilog HDL
• VLSI Design and Implementation of Code Convertors using VHDL/Verilog HDL
• VLSI Design and Implementation of Cell phone Controller using VHDL/Verilog HDL
• VLSI Design and Implementation of Bus Arbiter using VHDL/Verilog HDL
• VLSI Design and Implementation of Basic RSA Encryption Engine
• VLSI Design and Implementation of Basic DES Crypto Core
• VLSI Design and Implementation of Associate Memory using VHDL/Verilog HDL
• VLSI Design and Implementation of Arithmetic Logic Unit using VHDL/Verilog HDL
• VLSI Based Temperature Controller Implementation
• VLSI Based Motor Speed Controller
• VLSI Architecture and FPGA Prototyping of a Digital Camera for Image Security andAuthentication
• VHDL/Verilog HDL Implementation of Cordic Algorithm for Wireless LAN
• Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters
• The CSI Multimedia Architecture
• The Arise Approach for Extending Embedded Processors with Arbitrary Hardware Accelerators
• Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching
• System Architecture and Implementation of MIMO Sphere
• Superscalar Power Efficient Fast Fourier Transform FFT Architecture
• Spread Spectrum Image Watermarking with Digital Design
• Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits
• Power optimization of linear feedback shift Register (LFSR) for low power BIST
• Optimized Software Implementation of a Full-Rate IEEE 802.11a
• Novel Area-Efficient FPGA Architectures for FIR Filtering with Symmetric Signal Extension
• Matrix Multiplication Synthesis
• Low-Power Scan Testing for Test Data Compression Using A Routing-Driven Scan Architecture
• Low-Power Leading-Zero Counting and Anticipation Logic for High-Speed Floating Point Units
• Low Power Hardware Architecture for VBSME using Pixel Truncation
• Low Power Design of Precomputation-Based Content-Addressable Memory
• Left to Right Serial Multiplier for Large Numbers on FPGA
• L-Cbf: A Low-Power, Fast Counting Bloom Filter Architecture using VHDL/Verilog HDL
• Improving Error Tolerance for Multithreaded Register Files
• Improvement of the Orthogonal Code Convolution Capabilities using FPGA Implementation
• Implementation of Scramblers and Descramblers in Fiber Optic Communication Systems – SONET and OTN
• Implementation of Matched Filters Frequency Spectrum in Code Division Multiple Access(CDMA) System and its Implementation
• Implementation of IEEE 802.11 a WLAN baseband Processor
• Implementation of Hash Algorithm Used for Cryptography And Security
• Implementation of Data Link Layer Transmitter in PCI Express
• Implementation of Data Link Layer Receiver in PCI Express
• Implementation of Content Addressable Memory for ATM Applications
• Implementation of a Multi-Coder Processor for the WTLS with High Compression Ratio
• Implementation of a Multi-Channel UART Controller based on FIFO Technique and FPGA
• Implementation Huffman Coding For Bit Stream Compression In Mpeg – 2
• Implementation Five – Stage Pipelined RISC Processor for Parallel Processing
• High Definition Television (HDTV) Data Encoding and Decoding using Reed Solomon Code
• Hardware Algorithm for Variable Precision Multiplication on FPGA
• Fuzzy based PID Controller using VHDL/Verilog HDL/VERILOG for Transportation Application
• FPGA Implementation of USB Transceiver Macro-cell Interface with Usb2.0 Specifications
• FPGA Implementation of Low Power Parallel Multiplier
• FPGA Implementation of a Scalable Encryption Algorithm
• FPGA Based Power Efficient Channelizer for Software Defined Radio
• FPGA based Generation of High Frequency Carrier for Pulse Compression Using Cordic Algorithm
• Filter for Better Noise Performance
• Fault Secure Encoder and Decoder for Nano-memory Applications
• Enhancement Of Fault Injection Techniques Based On The Modification Of VHDL/Verilog HDL Code
• Emotion Recognition using Facial Expressions
• Deviation-Based LFSR Reseeding for Test-Data Compression
• Designing of Universal Sync / Async Receiver and Transmitter (USART)
• Designing of Risc Controller using Verilog HDL
• Designing of Programmable Timer Interface (PTI) using Verilog HDL
• Designing of Programmable Peripheral Interface (PPI) using Verilog HDL
• Designing of PC Printer Port / Serial Port using Verilog HDL
• Designing of I2C Master Core / SPI Master Core using Verilog HDL
• Designing Efficient Online Testable Reversible Adders with New Reversible Gate
• Design Of Reversible Finite Field Arithmetic Circuits with Error Detection
• Design of Reconfigurable Coprocessor for Communication Systems
• Design of MPLS Router and Optimization of MPLS Path Restoration Technique using VLSI
• Design of Industrial Robot
• Design of Industrial PLC
• Design of GPS-GSM Mobile Navigator
• Design Of Advanced Encryption Standard Using VHDL/Verilog HDL
• Design of a Simulator Tool for a Channel with Rayleigh Fading and AWGN Communication
• Design Exploration of a Spurious Power Suppression Technique (SPST) and its Applications
• Design and Synthesis of Programmable Logic Block with Mixed LUT and Macrogate
• Design and Simulation of Synchronization Unit for WCDMA Uplink Receiver
• Design and Implementation of Traffic Light Controller
• Design and Implementation of Mp4 Decoders On FPGA
• Design and Implementation of Elevator Controller
• Design and Implementation of Arithmetic Logic Unit using VHDL/Verilog HDL
• Custom Floating-Point Unit Generation for Embedded Systems
• Cost-Efficient SHA Hardware Accelerators
• Compliant Digital Baseband Transmitter on a Digital Signal Processor
• A Low-Power Low-Area Multiplier Based on Shift-and- Add Architecture
• Block-Based Multi-period Dynamic Memory Design for Low Data-Retention Power
• Bit-Swapping LFSR and Scan-Chain Ordering: A Novel Technique for Peak- and Average-Power Reduction In Scan-Based BIST
• Behavioral Synthesis of Asynchronous Circuits using Syntax Directed Translation as Backend
• Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication
• Area-Efficient Arithmetic Expression Evaluation using Deeply Pipelined Floating Point Cores Using VHDL/Verilog HDL
• An improved RC6 algorithm with the same structure of encryption and decryption
•
>An FPGA-Based Architecture for Real Time Image Feature Extraction
• An Area-Efficient Universal Cryptography Processor for Smart Cards
• VLSI Architecture for Visible Watermarking In A Secure Still Digital Camera (S2dc) Design
• VHDL/Verilog HDL Model of a IEEE1451.2 Smart Sensor: Characterization and Applications
• Verilog Implementation of UART Design with BIST Capability
• Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems
• Robust UART Architecture based on Recursive Running Sum
• Novel Multiplexer Based Truncated Array Multiplier
• Low Power Test Pattern Generator using A Variable-Length Ring Counter
• High-Speed Architecture for Reed-Solomon Decoder
• Low-Power Multiplier with the Spurious Power Suppression Technique
• Lossless Data Compression and Decompression Algorithm and its Hardware Architecture
• Generalization of a Fast RNS Conversion for a New 4-Modulus Base
• Full-Adder-Based Methodology for the Design of Scaling Operation In Residue Number System
• Framework for Correction of Multi-Bit Soft Errors in L2 Caches based on Redundancy
• Fast VLSI Design of Sms4 Cipher Based On Twisted BDD SBox Architecture
• Fast Hardware Approach for Approximate, Efficient Logarithm and Anti-logarithm Computations
• Compact AES Encryption Core for FPGA
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