Searching in Google

                We always looked up to google for our academic works, whether it be assignments or seminars or presentation materials or help with projects or what ever else you could think about.We could save a lot of time on googling if we google the thinks we need the right way.

   Heres one way that helped me save a bit of time finding materials on google.

             Generally we look for material in specific format whether it be doc or pdf or ppt. We could narrow down the search results by following a simple searching term.

             For example if we are looking for pdf file on specific subject like signed arithmetic. We could do it by modifying the search term to "filetype:pdf signed arithmetic " This will narrow down the search results to only pdf files that have words signed or arithmetic or both.

Heres the example

So to find doc file its filetype:doc signed arithmetic
     to find  ppt file its filetype:ppt signed arithmetic

                   

              Also there is an interesting search tool in google that is google scholar  which will help us in collecting materials for academic purpose. We could narrow down search results based on author names or title or date of publication etc.

Screenshot of Residue Number System search result on Google Scholar .

                     Its always good to collect material from known and trusted sites rather than beating around the bush. But there is nothing wrong in spending sometime googling for it.

       

Career in FPGAs

Read an interesting article on a technical forum electronicsforu about avenue into the field of FPGAs.

For those who don't know what FPGA is - it stands for Field Programmable Gate Array(FPGA) , is an integrated circuit designed to be configured by a customer or a designer after manufacturing—hence "field-programmable".


Here are some of the highlights from the article.

            As per semiconductor industry data, the total global programmable market was worth close to $5.1 billion in 2011, with $4 billion coming from FPGAs.

            India will grow as a market for engineers equipped with FPGA skillset. In the coming years, engineers equipped with FPGA skillset will be in demand at two levels—technology/block development and implementation.

          There is scope for career in  FPGA field not only in  manufacturing of these , but also working for organisations that design around FPGAs. These include Cisco, Juniper, Samsung and Tejas Networks. Firms like National Instruments, Wipro and Infosys too have divisions for FPGA engineers.

          A professor from IIT Bombay explains the role of an FPGA engineer: “A fresher’s job will involve activities like testing, emulation and verification, while an expert in FPGA will be asked to handle digital system design, system-on-chip, embedded hardware-software co-design, digital communication sub-systems, hardware accelerators for various computing tasks, embedded control systems and digital signal processing sub-systems/systems.”

Payscales for FPGA skill sets

Some of the Institutes that offer training in this field are Sandeepani , Veda-iit , CDAC .

You can read the complete article by clicking on this link.

VLSI Training Institutes

Here I am posting some links related to the VLSI courses. I have searched on net and came to know the best opportunities available. 
            If you guys know any good institutes please mention them in comments.. 

Enjoy your life at every moment

           Once a fisherman was sitting near seashore, under the shadow of a tree smoking his beedi. Suddenly a rich businessman passing by approached him and enquired as to why he was sitting under a tree smoking and not working. To this the poor fisherman replied that he had caught enough fishes for the day.

Hearing this the rich man got angry and said: Why don’t you catch more fishes instead of sitting in shadow wasting your time?

Fisherman asked: What would I do by catching more fishes?

Businessman: You could catch more fishes, sell them and earn more money, and buy a bigger boat.

Fisherman: What would I do then?

Businessman: You could go fishing in deep waters and catch even more fishes and earn even more money.

Fisherman: What would I do then?

Businessman: You could buy many boats and employ many people to work for you and earn even more money.

Fisherman: What would I do then?

Businessman: You could become a rich businessman like me.

Fisherman: What would I do then?

Businessman: You could then enjoy your life peacefully.

Fisherman: Isn’t that what I am doing now?

Moral – You don’t need to wait for tomorrow to be happy and enjoy your life. You don’t even need to be more rich, more powerful to enjoy life. LIFE is at this moment, enjoy it fully.

As some great men have said “My riches consist not in extent of my possessions but in the fewness of my wants”.

Xilinx tips and tricks

Problem1: ISE does not start

Solution:

  Clean up the project files. In order to do that go to "Project>Cleanup Project Files" as instructed in the following picture and in pop-up click ok. Note that this will delete those files instead of just removing them from your project.

  Open the task manager, kill redundant ISE processes. Press Alt-Ctrl-Del and look in the processes tab for "ise.exe". If there are more than one instances the chances are that something is wrong. Kill one of them.

Problem2: Whenever I try to add a file to the project, I get a weird error.

Solution: Make sure there are no spaces in the project path and the path of the file you want to add (Desktop is a symbolic link to C:\Documents and Settings\user_name\Desktop and therefore has spaces; avoid it). Xilinx is notorious for not being able to parse paths containing spaces. So don't ask for trouble.

Problem3: Whenever I start ISE simulator the clock is set to high impedance (Z) even if I have properly set it up.

Solution: It seems like you are simulating the wrong file. Make sure that the testbench is selected in your sources window and not the UUT (unit under test).

Problem4: My simulation starts correctly but I can not observe the internal signals of my UUT?

Solution: To add the signals you need choose the module first. The signals objects related to this module is displayed under the objects window. Then right click on the signals of your choice and click "Add to Wave Window". Altenatively you can drag and drop the signals to the Simulation/Waveform window. If you want to select all the signals of a module right click on a module in the Instances tab and click "Add to the Wave Window". If you want to view the data bus values in hex instead of binary, right click on the signal in the wave window. Select �Radix->Hexadecimal�.

Problem5: Place and Route fails with ERROR:Par:228 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint.

Solution: The timing constraints you have set are too tight and impossible to meet. You need either to set higher period target in your timing constraints.

Problem6: Random Xilinx weirdness. While you work Xilinx reports an error and dies immediately.

Solution: Many things could have gone wrong. The most common one is that the tool has corrupted your project files. In this case, it is better to give up on your current project and start a new one from the beginning. Open a previous project (.ise file) which you know to be working and start a new project by adding the .v files you used. You should always prefer to add and copy the sources of the files into your project ( "Add Copy of Source" over "Add source" when you right click on the project ).

Problem7: How do I save the ISIM settings and automatically load it?

Solution: As seen in the picture below, suppose you change the radix so that the values in the waveform are shown in decimal.

In order to make this a default part of my simulation,

1. First saved the Wave Configuration file (wcfg) to the hard drive by using the "save as" option under the file menu.

2. Back in ISE, under simulation source, right click on "Simulate Behavioral Model", choose "Process Properties"

3. Enable "Use Custom Waveform Configuration File"

4. Under "Custom Waveform Configuration File" use browse to select the file you saved your configuration to in ISIM

5. Click ok to close the dialog and you are done.

On your next simulation, you should see the results displayed using the setting you saved.

SystemVerilog

SystemVerilog is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, and reusability of Verilog based code. SystemVerilog brings a higher level of abstraction to design and verification. The language enhancements in SystemVerilog provide more concise hardware descriptions, while still providing an easy route with existing tools into current hardware implementation flows.

SystemVerilog provides a complete verification environment, employing Directed and Constraint Random Generation, Assertion Based Verification and Coverage Driven Verification. These methods improve the verification process dramatically.

SystemVerilog also provides enhanced hardware-modeling features, which improve the RTL design productivity and simplify the design process.       

Advantages of Using SystemVerilog:

» SystemVerilog was adopted as a standard by the Accellera organization, and is approval by IEEE. These ensure a wide embracing and support by multiple vendors of EDA tools and verification IP's, as well as interoperability between different tools and vendors.

» Since SystemVerilog is an extension of the popular Verilog language, the adoption process of SystemVerilog by engineers is extremely easy and straightforward. SystemVerilog enables engineers to adopt a modular approach for integrating new modules into any existing code. As a result, the risks and costs of adopting a new verification language are reduced.

» Being an integrated part of the simulation engine, eliminates the need for external verification tools and interfaces, and thus ensures optimal performance (running at least x2 faster than with any other verification languages).

» SystemVerilog brings a higher level of abstraction to the Verilog designer. Constructs and commands like Interfaces, new Data types (logic, int), Enumerated types, Arrays, Hardware-specific always (always_ff, always_comb) and others allow modeling of RTL designs easily, and with less coding.

» SystemVerilog extends the modeling aspects of Verilog by adding a Direct Programming Interface which allows C, C++, SystemC and Verilog code to work together without the overhead of the Verilog PLI.

Dynamic Arrays

Why Dynamic Arrays       Verilog allows one-dimensional arrays of variables all along and Verilog-2001 allows multi-dimensional ones too. SystemVerilog classifies an array as 'packed' or 'unpacked' depending on how it is declared. If the array upper and lower bounds are declared between the variable type and the variable name, such as reg [7:0] a_reg_array; The array is called packed. If the array bounds are declared after the variable name, it is called an unpacked array, such as, int int_array [7:0]; Of course, an array may have both packed and unpacked parts. reg [7:0] reg_array [3:0][7:0]; Whether you are declaring packed or unpacked arrays of whatever dimensions, one thing that remains common is they are all static declarations. Once an array is declared this way, the tool that parses the declaration will statically allocate memories for the array and there is no way that you can alter that afterwards. As a result, the size of an array, for example, cannot be changed once it is declared. There are occasions, however, when you would want to declare an array whose size cannot be pre-determined. A temporary buffer for variable rate incoming data stream, a list that has variable number of elements are few examples of problems that need array size that needs to be changed dynamically. Using a very large array with the assumption that it can hold the largest data (yet whose size is unknown) is neither safe nor efficient. So, the question is how can we declare an array whose size is dynamically alterable? SystemVerilog dynamic array type addresses this need. In a sense, dynamic arrays are equivalent of malloc library function in C that allows one to dynamically alter the size of an array (or pointer). Declaring a Dynamic Array             A dynamic array lets you keep the number of elements in the array unspecified at the declaration time. You can define the number of elements it holds during run time. Moreover, once declared, the number of elements can be altered at a later point of time too. However, these benefits come at a price. There are some limitations on dynamic arrays. These limitations are: The dynamic part of the array must be of unpacked nature. A packed array cannot be dynamic (can you guess why?)

TRANSPOSE OF A MATRIX

The following code is to get the transpose of a matrix. I have taken a simple 2x2 matrix. The logic in finding the transpose is similar to the logic in C. The code is written using procedural statements. The $display functions are used for the output display. The testbench for the program is also provided after the code.

Code:

module mat_add(

 input clk,

 input [7:0] in_1,

 input [7:0] in_2,

 input [7:0] in_3,

 input [7:0] in_4,

 output  [31:0] given_in,

 output  [31:0] trans_out

);

wire [7:0] temp [1:0][1:0];

wire [7:0] trans_temp [1:0][1:0];

genvar ROW,COLUMN;

assign temp[0][0] = in_1;

assign temp[0][1] = in_2;

assign temp[1][0] = in_3;

assign temp[1][1] = in_4;

for (COLUMN=0;COLUMN<2;COLUMN=COLUMN+1) begin

for (ROW=0;ROW<2;ROW=ROW+1) begin

assign trans_temp[COLUMN][ROW] = temp[ROW][COLUMN];

end

end

initial

begin

#100$display("the original matrix");

#100$display("%b\t %b",temp[0][0],temp[0][1]);

#100$display("%b\t %b",temp[1][0],temp[1][1]);

#100$display("the transposed matrix");

#100$display("%b\t %b",trans_temp[0][0],trans_temp[0][1]);

#100$display("%b\t %b",trans_temp[1][0],trans_temp[1][1]);

end

assign given_in = {{temp[1][1]},{temp[1][0]},{temp[0][1]},{temp[0][0]}};

assign trans_out = {trans_temp[0][0],trans_temp[0][1],trans_temp[1][0],trans_temp[1][1]};

endmodule

Testbench:

module matrix_transpose_test;

                // Inputs

                reg clk;

                reg [7:0] in_1;

                reg [7:0] in_2;

                reg [7:0] in_3;

                reg [7:0] in_4;

                // Outputs

                wire [31:0] given_in;

                wire [31:0] trans_out;

                // Instantiate the Unit Under Test (UUT)

                mat_add uut (

                                .clk(clk),

                                .in_1(in_1),

                                .in_2(in_2),

                                .in_3(in_3),

                                .in_4(in_4),

                                .given_in(given_in),

                                .trans_out(trans_out)

                );

                initial begin

                                // Initialize Inputs

                                clk = 0;

                                in_1 = 0;

                                in_2 = 0;

                                in_3 = 0;

                                in_4 = 0;

                                // Wait 100 ns for global reset to finish

                                #100;

                                clk = 1;

                                in_1 = 8'd12;

                                in_2 = 8'd23;

                                in_3 = 8'd45;

                                in_4 = 8'd32;

                                // Add stimulus here

                end

      endmodule

Output:

the original matrix

00001100     00010111

00101101     00100000

the transposed matrix

00001100    00101101

00010111    00100000

Example of multidimensional array

The following code is a best example for declaring a multi-dimensional array. It gives you an idea on how to declare a one dimensional and a two dimensional array. The code is based on system verilog which allows you to declare an array without specifying the length (in the following code reg [15:0] len_type []). 

module multidimensional_array();

reg [7:0] preamble [0:6] = '{8'hAA,8'hAA,8'hAA,8'hAA,8'hAA,8'hAA,8'hAA};

reg [7:0] dest_src_addr [0:1] [0:5] = '{'{8'h0,8'h1,8'h2,8'h3,8'h4,8'h5},'{8'h6,8'h7,8'h8,8'h9,8'hA,8'hB}};

reg [15:0] len_type [];

initial begin

$display("example of multidimensional array\n");

$display ("preamble[0]= %b", preamble[0]);

$display ("preamble[1][0]= %b", preamble[1][0]);

$display ("dest_src_addr[0][1]= %b", dest_src_addr[0][1]);

$display ("dest_src_addr[1][1]= %b\n", dest_src_addr[1][1]);

len_type = new[2];

for ( int i = 0; i < 2; i ++)

begin

len_type[i] = i;

end

#1 $finish;

end

endmodule

Output :

Example of multidimensional array

preamble[0]= 10101010

preamble[1][0]= 0

dest_src_addr[0][1]= 00000001

dest_src_addr[1][1]= 00000111

         Here is a simple notes on Verilog operators. It gives a brief details of all operators used in verilog. Hope this is useful.

Verilog Operators..

verilog notes....

Digital design principles and practices by john f wakerly.pdf

It's Inspiring

I was in an audience listening to a motivational guru. The speaker whipped out his wallet and pulled out a five hundred rupee note. Holding it up, he asked, “Who wants this five hundred rupee note?”

          Lots of hands went up. Including mine. A slow chorus began to build as people began to shout “Me!” “Me!”I began to wonder who the lucky one would be who the speaker would choose. And I also secretly wondered – and I am sure others did too - why he would simply give away five hundred rupees.

          Even as the shouts of “I want it” grew louder, I noticed a young woman running down the aisle. She ran up onto the stage, went up to the speaker, and grabbed the five hundred rupee note from his hand. “Well done, young lady,” said the speaker into

Let go off your Stress

A psychologist walked around a room while teaching stress management to an audience. As she raised a glass of water, everyone expected they’d be asked the “half empty or half full” question. Instead, with a smile on her face, she inquired: “How heavy is this glass of water?”

She replied, “The absolute weight doesn’t matter. It depends on how long I hold it. If I hold it for a minute, it’s not a problem. If I hold it for an hour, I’ll have an ache in my arm. If I hold it for a day, my arm will feel numb and paralyzed. In each case, the weight of the glass doesn’t change, but the longer I hold it, the heavier it becomes.”

She continued, “The stresses and worries in life are like that glass of water. Think about them for a while and nothing happens. Think about them a bit longer and they begin to hurt. And if you think about them all day long, you will feel paralyzed – incapable of doing anything.”

It’s important to remember to let go of your stresses. As early in the evening as you can, put all your burdens down. Don’t carry them through the evening and into the night. Remember to put the glass down!

Solving error in xilinx

How to solve the following error in Xilinx ISE:
"Simulator: 702 – Can’t find design unit xxx in library work located at isim/work"
You can try two methods to solve this error:

1) Go to main menu -> Project -> Cleanup Project files. Click 'ok'. Now run the simulation again. If the error is still on then go to step 2.

  Note:-Cleaning up project files removes the generated synthesis and implementation files from the current project directory. This operation is final and you can not undo this procedure after you perform it. If you want to avoid loss of data, then create a backup copy of the project. For creating a backup for your project:
    Select Project > Take Snapshot. 
    In the Take a Snapshot of the Project dialog box, enter a name for your snapshot in the Snapshot Name field.
    In the Comment field, add any notes related to this version of your project. Comments are optional.
    Click OK.

2) Create a new project and add all the files in your current project to the new project.Now simulate the design. It should work now.

3-to-8 DECODER

The following code is a 3-to-8 decoder which takes a 3 bit input and gives an 8 bit output. I have represented all the possible output using one hot code. The program is written using non-blocking statements and using case statements.

Code:

module decoder_3_to_8(

input [2:0] i,

output reg[7:0] decoder_output

    );

                 // declaring parameters

                 parameter  OUT_1 = 8'b00000001;

                 parameter  OUT_2 = 8'b00000001;

                 parameter  OUT_3 = 8'b00000100;

                 parameter  OUT_4 = 8'b00001000;

                 parameter  OUT_5 = 8'b00010000;

                 parameter  OUT_6 = 8'b00100000;

                 parameter  OUT_7 = 8'b01000000;

                 parameter  OUT_8 = 8'b10000000;

                 parameter  DETAULT_OUT = 8'bxxxxxxxx;

                

always@(*)

begin

case(i)

3'b000: decoder_output<= OUT_1;

3'b001: decoder_output<= OUT_2;

3'b010: decoder_output<= OUT_3;

3'b011: decoder_output<= OUT_4;

3'b100: decoder_output<= OUT_5;

3'b101: decoder_output<= OUT_6;

3'b110: decoder_output<= OUT_7;

3'b111: decoder_output<= OUT_8;

default:decoder_output<= DETAULT_OUT;

endcase

end

endmodule

ADDER USIGN DECODER

This code shows how full adder can be implemented using a decoder (3-to-8). I am using instantiation method to do this. I am instantiating the decoder (3_to_8) in the main module.  The code for the decoder is available in other posts..

module adder_using_decoder(

input a,b,c_in,

output sum,c_out

    );

           wire[7:0] sum_connector;              //declaring an intermediate wire

// instantiating the decoder

           decoder_3_to_8 dc (

    .i({a,b,c_in}), 

    .decoder_output(sum_connector)

    );

assign sum= { sum_connector[1] | sum_connector[2] | sum_connector[4] | sum_connector[7]};

assign c_out = {sum_connector[3]|sum_connector[5]|sum_connector[6]|sum_connector[7]};

endmodule

GRAY TO BINARY CONVERTER

This program is to convert gray code to binary code. The logic behind conversion is the most significant bit is same and the consequent bits are the result of ex-or of gray and binary bits. 

  

module bin_to_gray(

input clk,

input [2:0]gray_input,

output reg [2:0]bin_out

);

always@(posedge clk)

begin

bin_out[2] <= gray_input[2];

bin_out[1] <= bin_out[2] ^ gray_input[1];

bin_out[0] <= bin_out[1] ^ gray_input[0];

end

endmodule

BINARY TO GRAY CONVERTER

This program is to convert binary number into gray code. The logic behind conversion is the most significant bit is same and the consequent bits are the result of ex-or of binary bits.  

module bin_to_gray(

input clk,

input [2:0]binary,

output reg[2:0]gray

);

always@(posedge clk)

begin

gray[2] = binary[2];

gray[1] = binary[2] ^ binary[1];

gray[0] = binary[1] ^ binary[0];

end

endmodule

Reversing the Bits

 This program is to reverse a bit stream. In this example I have taken a 4 bit no. If you give an input like 0011, the output will be 1100.


module rev_mod(
input [WIDTH:0]in,
output reg [WIDTH:0] y
);
 

parameter WIDTH=3;
integer i;

always@(*)
begin
for(i=0; i<=WIDTH; i=i+1)
begin
y [WIDTH-i] = in[i];
end
#200  $display("y %b\t in %b",y,in);
end
endmodule 
  

Verilog program for ENCODER (8-to-3)

module encoder_8_to_3(

input [7:0] i,
output reg [2:0] out

    );

always@(*)
begin
case(i)

8'b00000001: out <= 3'b000;
8'b00000010: out <= 3'b001;
8'b00000100: out <= 3'b010;
8'b00001000: out <= 3'b011;
8'b00010000: out <= 3'b100;
8'b00100000: out <= 3'b101;
8'b01000000: out <= 3'b110;
8'b10000000: out <= 3'b111;
default: out<= 3'bxxx;

endcase
end
endmodule

ADDER USING 4-TO-1 MUX

module adder_using_4to1_mux(

                             input [1:0]ab,input carry_in,clk,

                             output reg sum,carry_out

    );

           

          /// declaring parameter

parameter  SEL_LINE_1 = 2'b00;

parameter  SEL_LINE_2 = 2'b01;

parameter  SEL_LINE_3 = 2'b10;

parameter  SEL_LINE_4 = 2'b11;

           

           

always@(*)                         // (*) means sensitivity list contains all the right side values

begin

if(ab==SEL_LINE_1) begin

          sum <= carry_in;

          carry_out <= 0; end

          else if(ab==SEL_LINE_2) begin

          sum <= ~carry_in;

          carry_out <= carry_in; end

          else if(ab==SEL_LINE_3) begin

          sum <= ~carry_in;

          carry_out <= carry_in; end

else

          begin

          sum <= carry_in;

          carry_out <= 1;

          end

end

endmodule

Verilog program for MOD-10 COUNTER

The program is for a mod 10 counter.

module counter(

input clk,rst,enable,

output reg [3:0]counter_output

);

always@ (posedge clk)

begin 

if( rst | counter_output==4'b1001)

counter_output <= 4'b0000;

else if(enable)

counter_output <= counter_output + 1;

else

counter_output <= 0;

end

endmodule

Verilog program for a DECODER

      Here i am assuming a 3-to-8 decoder. Hence for a 3-to-8 decoder the input will be a 3 bit no ([2:0]i) and output will be a 8 bit no ([7:0]decoder_output). Care should be taken that the module name should not start with number like 3_to_8_decoder. 

module decoder_3_to_8(

input [2:0] i,

output reg[7:0] decoder_output

    );

// declaring parameters

parameter  OUT_1 = 8'b00000001;  

parameter  OUT_2 = 8'b00000001;

parameter  OUT_3 = 8'b00000100;

parameter  OUT_4 = 8'b00001000;

parameter  OUT_5 = 8'b00010000;

parameter  OUT_6 = 8'b00100000;

parameter  OUT_7 = 8'b01000000;

parameter  OUT_8 = 8'b10000000;

parameter  DETAULT_OUT = 8'bxxxxxxxx;

 

always@(*)

begin 

case(i)

3'b000: decoder_output<= OUT_1;

3'b001: decoder_output<= OUT_2;

3'b010: decoder_output<= OUT_3;

3'b011: decoder_output<= OUT_4;

3'b100: decoder_output<= OUT_5;

3'b101: decoder_output<= OUT_6;

3'b110: decoder_output<= OUT_7;

3'b111: decoder_output<= OUT_8;

default:decoder_output<= DETAULT_OUT;

endcase

end

endmodule