The
program is for a mod 10 counter.
module counter(
input clk,rst,enable,
output reg [3:0]counter_output
);
always@ (posedge clk)
begin
if( rst | counter_output==4'b1001)
counter_output <= 4'b0000;
else if(enable)
counter_output <= counter_output + 1;
else
counter_output <= 0;
end
endmodule
2 comments:
Can you please give the test bench
module mod_10_counter_test;
// Inputs
reg clk;
reg rst;
reg enable;
// Outputs
wire [3:0] counter_output;
// Instantiate the Unit Under Test (UUT)
counter uut (
.clk(clk),
.rst(rst),
.enable(enable),
.counter_output(counter_output)
);
always
#50 clk= ~ clk;
initial begin
clk=0;
// Initialize Inputs
rst = 0;
enable = 0;
#100;
rst=0;
enable=1;
#100;
rst=0;
enable=1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule
Post a Comment