module
adder_using_4to1_mux(
input [1:0]ab,input
carry_in,clk,
output reg
sum,carry_out
);
/// declaring parameter
parameter SEL_LINE_1 = 2'b00;
parameter SEL_LINE_2 = 2'b01;
parameter SEL_LINE_3 = 2'b10;
parameter SEL_LINE_4 = 2'b11;
always@(*) // (*) means
sensitivity list contains all the right side values
begin
if(ab==SEL_LINE_1)
begin
sum <= carry_in;
carry_out <= 0; end
else if(ab==SEL_LINE_2) begin
sum <= ~carry_in;
carry_out <= carry_in; end
else if(ab==SEL_LINE_3) begin
sum <= ~carry_in;
carry_out <= carry_in; end
else
begin
sum <= carry_in;
carry_out <= 1;
end
end
endmodule
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