Verilog program for a DECODER

      Here i am assuming a 3-to-8 decoder. Hence for a 3-to-8 decoder the input will be a 3 bit no ([2:0]i) and output will be a 8 bit no ([7:0]decoder_output). Care should be taken that the module name should not start with number like 3_to_8_decoder. 

module decoder_3_to_8(

input [2:0] i,

output reg[7:0] decoder_output

    );

// declaring parameters

parameter  OUT_1 = 8'b00000001;  

parameter  OUT_2 = 8'b00000001;

parameter  OUT_3 = 8'b00000100;

parameter  OUT_4 = 8'b00001000;

parameter  OUT_5 = 8'b00010000;

parameter  OUT_6 = 8'b00100000;

parameter  OUT_7 = 8'b01000000;

parameter  OUT_8 = 8'b10000000;

parameter  DETAULT_OUT = 8'bxxxxxxxx;

 

always@(*)

begin 

case(i)

3'b000: decoder_output<= OUT_1;

3'b001: decoder_output<= OUT_2;

3'b010: decoder_output<= OUT_3;

3'b011: decoder_output<= OUT_4;

3'b100: decoder_output<= OUT_5;

3'b101: decoder_output<= OUT_6;

3'b110: decoder_output<= OUT_7;

3'b111: decoder_output<= OUT_8;

default:decoder_output<= DETAULT_OUT;

endcase

end

endmodule