TRANSPOSE OF A MATRIX

The following code is to get the transpose of a matrix. I have taken a simple 2x2 matrix. The logic in finding the transpose is similar to the logic in C. The code is written using procedural statements. The $display functions are used for the output display. The testbench for the program is also provided after the code.

Code:

module mat_add(

 input clk,

 input [7:0] in_1,

 input [7:0] in_2,

 input [7:0] in_3,

 input [7:0] in_4,

 output  [31:0] given_in,

 output  [31:0] trans_out

);

wire [7:0] temp [1:0][1:0];

wire [7:0] trans_temp [1:0][1:0];

genvar ROW,COLUMN;

assign temp[0][0] = in_1;

assign temp[0][1] = in_2;

assign temp[1][0] = in_3;

assign temp[1][1] = in_4;

for (COLUMN=0;COLUMN<2;COLUMN=COLUMN+1) begin

for (ROW=0;ROW<2;ROW=ROW+1) begin

assign trans_temp[COLUMN][ROW] = temp[ROW][COLUMN];

end

end

initial

begin

#100$display("the original matrix");

#100$display("%b\t %b",temp[0][0],temp[0][1]);

#100$display("%b\t %b",temp[1][0],temp[1][1]);

#100$display("the transposed matrix");

#100$display("%b\t %b",trans_temp[0][0],trans_temp[0][1]);

#100$display("%b\t %b",trans_temp[1][0],trans_temp[1][1]);

end

assign given_in = {{temp[1][1]},{temp[1][0]},{temp[0][1]},{temp[0][0]}};

assign trans_out = {trans_temp[0][0],trans_temp[0][1],trans_temp[1][0],trans_temp[1][1]};

endmodule

Testbench:

module matrix_transpose_test;

                // Inputs

                reg clk;

                reg [7:0] in_1;

                reg [7:0] in_2;

                reg [7:0] in_3;

                reg [7:0] in_4;

                // Outputs

                wire [31:0] given_in;

                wire [31:0] trans_out;

                // Instantiate the Unit Under Test (UUT)

                mat_add uut (

                                .clk(clk),

                                .in_1(in_1),

                                .in_2(in_2),

                                .in_3(in_3),

                                .in_4(in_4),

                                .given_in(given_in),

                                .trans_out(trans_out)

                );

                initial begin

                                // Initialize Inputs

                                clk = 0;

                                in_1 = 0;

                                in_2 = 0;

                                in_3 = 0;

                                in_4 = 0;

                                // Wait 100 ns for global reset to finish

                                #100;

                                clk = 1;

                                in_1 = 8'd12;

                                in_2 = 8'd23;

                                in_3 = 8'd45;

                                in_4 = 8'd32;

                                // Add stimulus here

                end

      endmodule

Output:

the original matrix

00001100     00010111

00101101     00100000

the transposed matrix

00001100    00101101

00010111    00100000

Example of multidimensional array

The following code is a best example for declaring a multi-dimensional array. It gives you an idea on how to declare a one dimensional and a two dimensional array. The code is based on system verilog which allows you to declare an array without specifying the length (in the following code reg [15:0] len_type []). 

module multidimensional_array();

reg [7:0] preamble [0:6] = '{8'hAA,8'hAA,8'hAA,8'hAA,8'hAA,8'hAA,8'hAA};

reg [7:0] dest_src_addr [0:1] [0:5] = '{'{8'h0,8'h1,8'h2,8'h3,8'h4,8'h5},'{8'h6,8'h7,8'h8,8'h9,8'hA,8'hB}};

reg [15:0] len_type [];

initial begin

$display("example of multidimensional array\n");

$display ("preamble[0]= %b", preamble[0]);

$display ("preamble[1][0]= %b", preamble[1][0]);

$display ("dest_src_addr[0][1]= %b", dest_src_addr[0][1]);

$display ("dest_src_addr[1][1]= %b\n", dest_src_addr[1][1]);

len_type = new[2];

for ( int i = 0; i < 2; i ++)

begin

len_type[i] = i;

end

#1 $finish;

end

endmodule

Output :

Example of multidimensional array

preamble[0]= 10101010

preamble[1][0]= 0

dest_src_addr[0][1]= 00000001

dest_src_addr[1][1]= 00000111

         Here is a simple notes on Verilog operators. It gives a brief details of all operators used in verilog. Hope this is useful.

Verilog Operators..

verilog notes....

Digital design principles and practices by john f wakerly.pdf

It's Inspiring

I was in an audience listening to a motivational guru. The speaker whipped out his wallet and pulled out a five hundred rupee note. Holding it up, he asked, “Who wants this five hundred rupee note?”

          Lots of hands went up. Including mine. A slow chorus began to build as people began to shout “Me!” “Me!”I began to wonder who the lucky one would be who the speaker would choose. And I also secretly wondered – and I am sure others did too - why he would simply give away five hundred rupees.

          Even as the shouts of “I want it” grew louder, I noticed a young woman running down the aisle. She ran up onto the stage, went up to the speaker, and grabbed the five hundred rupee note from his hand. “Well done, young lady,” said the speaker into

Let go off your Stress

A psychologist walked around a room while teaching stress management to an audience. As she raised a glass of water, everyone expected they’d be asked the “half empty or half full” question. Instead, with a smile on her face, she inquired: “How heavy is this glass of water?”

She replied, “The absolute weight doesn’t matter. It depends on how long I hold it. If I hold it for a minute, it’s not a problem. If I hold it for an hour, I’ll have an ache in my arm. If I hold it for a day, my arm will feel numb and paralyzed. In each case, the weight of the glass doesn’t change, but the longer I hold it, the heavier it becomes.”

She continued, “The stresses and worries in life are like that glass of water. Think about them for a while and nothing happens. Think about them a bit longer and they begin to hurt. And if you think about them all day long, you will feel paralyzed – incapable of doing anything.”

It’s important to remember to let go of your stresses. As early in the evening as you can, put all your burdens down. Don’t carry them through the evening and into the night. Remember to put the glass down!

Solving error in xilinx

How to solve the following error in Xilinx ISE:
"Simulator: 702 – Can’t find design unit xxx in library work located at isim/work"
You can try two methods to solve this error:

1) Go to main menu -> Project -> Cleanup Project files. Click 'ok'. Now run the simulation again. If the error is still on then go to step 2.

  Note:-Cleaning up project files removes the generated synthesis and implementation files from the current project directory. This operation is final and you can not undo this procedure after you perform it. If you want to avoid loss of data, then create a backup copy of the project. For creating a backup for your project:
    Select Project > Take Snapshot. 
    In the Take a Snapshot of the Project dialog box, enter a name for your snapshot in the Snapshot Name field.
    In the Comment field, add any notes related to this version of your project. Comments are optional.
    Click OK.

2) Create a new project and add all the files in your current project to the new project.Now simulate the design. It should work now.

3-to-8 DECODER

The following code is a 3-to-8 decoder which takes a 3 bit input and gives an 8 bit output. I have represented all the possible output using one hot code. The program is written using non-blocking statements and using case statements.

Code:

module decoder_3_to_8(

input [2:0] i,

output reg[7:0] decoder_output

    );

                 // declaring parameters

                 parameter  OUT_1 = 8'b00000001;

                 parameter  OUT_2 = 8'b00000001;

                 parameter  OUT_3 = 8'b00000100;

                 parameter  OUT_4 = 8'b00001000;

                 parameter  OUT_5 = 8'b00010000;

                 parameter  OUT_6 = 8'b00100000;

                 parameter  OUT_7 = 8'b01000000;

                 parameter  OUT_8 = 8'b10000000;

                 parameter  DETAULT_OUT = 8'bxxxxxxxx;

                

always@(*)

begin

case(i)

3'b000: decoder_output<= OUT_1;

3'b001: decoder_output<= OUT_2;

3'b010: decoder_output<= OUT_3;

3'b011: decoder_output<= OUT_4;

3'b100: decoder_output<= OUT_5;

3'b101: decoder_output<= OUT_6;

3'b110: decoder_output<= OUT_7;

3'b111: decoder_output<= OUT_8;

default:decoder_output<= DETAULT_OUT;

endcase

end

endmodule

ADDER USIGN DECODER

This code shows how full adder can be implemented using a decoder (3-to-8). I am using instantiation method to do this. I am instantiating the decoder (3_to_8) in the main module.  The code for the decoder is available in other posts..

module adder_using_decoder(

input a,b,c_in,

output sum,c_out

    );

           wire[7:0] sum_connector;              //declaring an intermediate wire

// instantiating the decoder

           decoder_3_to_8 dc (

    .i({a,b,c_in}), 

    .decoder_output(sum_connector)

    );

assign sum= { sum_connector[1] | sum_connector[2] | sum_connector[4] | sum_connector[7]};

assign c_out = {sum_connector[3]|sum_connector[5]|sum_connector[6]|sum_connector[7]};

endmodule

GRAY TO BINARY CONVERTER

This program is to convert gray code to binary code. The logic behind conversion is the most significant bit is same and the consequent bits are the result of ex-or of gray and binary bits. 

  

module bin_to_gray(

input clk,

input [2:0]gray_input,

output reg [2:0]bin_out

);

always@(posedge clk)

begin

bin_out[2] <= gray_input[2];

bin_out[1] <= bin_out[2] ^ gray_input[1];

bin_out[0] <= bin_out[1] ^ gray_input[0];

end

endmodule

BINARY TO GRAY CONVERTER

This program is to convert binary number into gray code. The logic behind conversion is the most significant bit is same and the consequent bits are the result of ex-or of binary bits.  

module bin_to_gray(

input clk,

input [2:0]binary,

output reg[2:0]gray

);

always@(posedge clk)

begin

gray[2] = binary[2];

gray[1] = binary[2] ^ binary[1];

gray[0] = binary[1] ^ binary[0];

end

endmodule

Reversing the Bits

 This program is to reverse a bit stream. In this example I have taken a 4 bit no. If you give an input like 0011, the output will be 1100.


module rev_mod(
input [WIDTH:0]in,
output reg [WIDTH:0] y
);
 

parameter WIDTH=3;
integer i;

always@(*)
begin
for(i=0; i<=WIDTH; i=i+1)
begin
y [WIDTH-i] = in[i];
end
#200  $display("y %b\t in %b",y,in);
end
endmodule 
  

Verilog program for ENCODER (8-to-3)

module encoder_8_to_3(

input [7:0] i,
output reg [2:0] out

    );

always@(*)
begin
case(i)

8'b00000001: out <= 3'b000;
8'b00000010: out <= 3'b001;
8'b00000100: out <= 3'b010;
8'b00001000: out <= 3'b011;
8'b00010000: out <= 3'b100;
8'b00100000: out <= 3'b101;
8'b01000000: out <= 3'b110;
8'b10000000: out <= 3'b111;
default: out<= 3'bxxx;

endcase
end
endmodule

ADDER USING 4-TO-1 MUX

module adder_using_4to1_mux(

                             input [1:0]ab,input carry_in,clk,

                             output reg sum,carry_out

    );

           

          /// declaring parameter

parameter  SEL_LINE_1 = 2'b00;

parameter  SEL_LINE_2 = 2'b01;

parameter  SEL_LINE_3 = 2'b10;

parameter  SEL_LINE_4 = 2'b11;

           

           

always@(*)                         // (*) means sensitivity list contains all the right side values

begin

if(ab==SEL_LINE_1) begin

          sum <= carry_in;

          carry_out <= 0; end

          else if(ab==SEL_LINE_2) begin

          sum <= ~carry_in;

          carry_out <= carry_in; end

          else if(ab==SEL_LINE_3) begin

          sum <= ~carry_in;

          carry_out <= carry_in; end

else

          begin

          sum <= carry_in;

          carry_out <= 1;

          end

end

endmodule

Verilog program for MOD-10 COUNTER

The program is for a mod 10 counter.

module counter(

input clk,rst,enable,

output reg [3:0]counter_output

);

always@ (posedge clk)

begin 

if( rst | counter_output==4'b1001)

counter_output <= 4'b0000;

else if(enable)

counter_output <= counter_output + 1;

else

counter_output <= 0;

end

endmodule

Verilog program for a DECODER

      Here i am assuming a 3-to-8 decoder. Hence for a 3-to-8 decoder the input will be a 3 bit no ([2:0]i) and output will be a 8 bit no ([7:0]decoder_output). Care should be taken that the module name should not start with number like 3_to_8_decoder. 

module decoder_3_to_8(

input [2:0] i,

output reg[7:0] decoder_output

    );

// declaring parameters

parameter  OUT_1 = 8'b00000001;  

parameter  OUT_2 = 8'b00000001;

parameter  OUT_3 = 8'b00000100;

parameter  OUT_4 = 8'b00001000;

parameter  OUT_5 = 8'b00010000;

parameter  OUT_6 = 8'b00100000;

parameter  OUT_7 = 8'b01000000;

parameter  OUT_8 = 8'b10000000;

parameter  DETAULT_OUT = 8'bxxxxxxxx;

 

always@(*)

begin 

case(i)

3'b000: decoder_output<= OUT_1;

3'b001: decoder_output<= OUT_2;

3'b010: decoder_output<= OUT_3;

3'b011: decoder_output<= OUT_4;

3'b100: decoder_output<= OUT_5;

3'b101: decoder_output<= OUT_6;

3'b110: decoder_output<= OUT_7;

3'b111: decoder_output<= OUT_8;

default:decoder_output<= DETAULT_OUT;

endcase

end

endmodule

VERILOG PROGRAM FOR LOGICAL OPERATIONS:

module logical_operation(

    input a_in,b_in,

           output reg or_out,and_out,xor_out,xnor_out

           );

assign a_in=1;

assign b_in=0;

always@(a_in,b_in)

begin

or_out <= a_in | b_in;

and_out <= a_in & b_in;

xor_out <= (a_in ^ b_in);

xnor_out <= (a_in ~^ b_in);

end

endmodule

Verilog Modules

Hello friends,

I am here again with a new post.

We are very familiar with verilog coding but still have so many doubts

It's really interesting to know new things and new ways of coding.

But to master in coding we need to have sufficient backup (data) with us.

So here I am providing some links which, I feel, are useful to us in improving our coding style and also help in clarifying our doubts regarding coding.

Use them and improve the coding style...

http://web.engr.oregonstate.edu/~traylor/ece474/lecture_verilog/beamer/verilog_modules.pdf