VERILOG PROGRAM FOR LOGICAL OPERATIONS:

module logical_operation(

    input a_in,b_in,

           output reg or_out,and_out,xor_out,xnor_out

           );

assign a_in=1;

assign b_in=0;

always@(a_in,b_in)

begin

or_out <= a_in | b_in;

and_out <= a_in & b_in;

xor_out <= (a_in ^ b_in);

xnor_out <= (a_in ~^ b_in);

end

endmodule